In the stand-alone and embedded semiconductor memory areas, as the memory density increases, the silicon area consumed by the memory needs to be reduced in order to remain cost-effective. Memory cell size is continuously being reduced to achieve such silicon area reduction. If the continued efforts in reducing the cell size is not accompanied with similar efforts in reducing the size of those periphery circuits which interface with the memory array, the silicon area consumed by the periphery circuit becomes the bottleneck in achieving smaller silicon area.
Row decoder circuit is one of the circuit blocks which interfaces with the memory array. Conventionally, the wordline (row) path of a memory includes address buffers driving row predecoding circuits which in turn drive the row decoder. The address buffer and row predecoding circuits are generally located in the periphery area of a memory and do not physically interface with the memory array. However, the row decoder usually extends along one side or through the center of the memory array. With a reduction in the cell size, the memory cell pitch within which the row decoder needs to be formed is equally reduced. Thus, to achieve an effective overall area reduction, the row decoder needs to be reduced in size.
Conventional row decoders include multi-decoding stages. In, for example, a three-stage row decoding scheme, a first decoding stage receives a first group of predecoded row address signals and in response selects a group of the decode logic in the second decoding stage. The second decoding stage, in addition to the signal(s) from the first decoding stage, receives a second set of predecoded row address signals and in response selects one of a group of wordline drivers which form the third decoding stage. This third decoding stage, in addition to the signal(s) from the second decoding stage, may receive a third set of predecoded row address signals and in response selects a wordline in one or more memory arrays.
Many row decoding schemes for minimizing the size of the row decoder, for example by reducing the number of transistors in one or more of the three decoding stages of the row decoder, have been proposed and used. Although such reduction in the number of transistors results in a smaller row decoder, no technique has been proposed which yields a substantial reduction in the silicon are consumed by the row decoder.
Thus, there is a need for a circuit technique and array configuration which yield a significant reduction in the silicon area consumed by the row decoder.
In accordance with an embodiment of the present invention, a semiconductor memory includes a memory array having a plurality of rows and columns of sectors, a horizontal global row decoder, a vertical global row decoder, and a plurality of horizontal local row decoders. Each of the sectors has a plurality of rows and columns of memory cells. The horizontal global row decoder is configured to select one of the rows of sectors in response to a first set of row address signals. The vertical global row decoder is configured to select one or two adjacent columns of the columns of sectors in response to a second set of row address signals. The plurality of horizontal local row decoders are coupled to the vertical global row decoder and the horizontal global row decoder to select one or two adjacent sectors located at the intersection of the selected row of sectors and the selected one or two adjacent columns of sectors.
In another embodiment, the semiconductor memory also includes a plurality of vertical local row decoders coupled to the plurality of horizontal local row decoders to select a row of memory cells in the selected one or two adjacent sectors in response to a third plurality of row address signals.
In accordance with another embodiment of the present invention, a semiconductor memory includes a memory array having a plurality of sectors each having a plurality of rows and columns of memory cells, a horizontal global row decoder, a vertical global row decoder, and a plurality of horizontal local row decoders. The horizontal global row decoder is configured to provide a first plurality of predecoded row address signals on a first plurality of lines extending across the memory array in a direction parallel to the rows of memory cells. The vertical global row decoder is configured to provide a second plurality of predecoded row address signals on a second plurality of lines extending across the memory array in a direction parallel to the columns of memory cells. The plurality of horizontal local row decoders are configured so that one of the plurality of horizontal local row decoders selects one or both of two sectors located adjacent to the one of the plurality of horizontal local row decoders in response to a unique combination of the first and second plurality of predecoded row address signals.
In another embodiment, the semiconductor memory further includes a plurality of vertical local row decoders configured to provide a third plurality of predecoded row address signals on a third plurality of lines extending across the memory array in a direction parallel to the columns of memory cells. The one of the plurality of horizontal local row decoders selecting one or both of two sectors located adjacent to the one of the plurality of horizontal local row decoders further selects a row of memory cells in the selected one or both of two sectors in response to the third plurality of predecoded row address signals.
In another embodiment, the vertical local row decoders are located along at least one side of the memory array, the vertical local row decoders being equal in number to the plurality of columns of horizontal local row decoders.
In another embodiment, each of the plurality of horizontal local row decoders includes a logic gate coupled to a decode circuit. The logic gate is configured to provide an output signal in response to a subset of the first plurality of signals and a subset of the second plurality of signals. The decode circuit is configured to provide a plurality of output signals in response to the output signal of the logic gate and the third plurality of predecoded row address signals.
In another embodiment, of the plurality of rows and columns of sectors, the logic gate in the one of the plurality of horizontal local row decoders operates to select the one or both of two sectors located adjacent to the one of the plurality of horizontal local row decoders in response to a preselected subset of each of the first and second plurality of predecoded row address signals. The decode circuit in the one of the plurality of horizontal local row decoders operates to select one of the rows of memory cells in the selected one or both of two sectors in response to the output signal of the logic gate and the third plurality of predecoded row address signals.
In another embodiment, the plurality of sectors are arranged along rows and columns, and the plurality of horizontal local row decoders are arranged along a plurality of rows and columns. Each column of the horizontal local row decoders separates two columns of sectors.